Traditionally, networking features and protocols in network devices have been implemented by hardware-dedicated ASIC designs. These fixed ASIC designs limit the rate of deployment of new protocols. Hardware changes to support new protocols are expensive in term of both cost and time. As a result, programmable networking devices which allow users to deploy new features and protocols by means of software are becoming more attractive.
An approach of the prior art for implementing new network protocols is to use software running on state-of-the-art general-purpose CPUs. However, the processing capacity of these general-purpose CPUs, currently at maximum of 64 bits, cannot guarantee real-time performance for current networking systems that support network packet flows up to 100 Gbps.
Another approach of the prior art for implementing new network protocols is to use reconfigurable FPGA chips. However, limitations in logic cell capacity of FPGA chips do not allow processing network packets with large sizes, such as hundreds of bytes, at full throughput. In addition, high complexity in internal interconnect wirings makes FPGA chips run at low frequency with high latency. These poor characteristics of FPGA chips are not appropriate for performing complex network features required in state-of-the-art enterprise and data-center networks.